Commit Graph

3 Commits

Author SHA1 Message Date
Jeong YunWon
d42c4eb21e move builtins module to vm::stdlib::builtlins for consistency 2021-10-01 01:54:04 +09:00
Jeong YunWon
c3d8e792b7 tp_ -> slot_ 2021-09-30 02:51:44 +09:00
Jeong YunWon
fb4581bd45 vm::sysmodule -> vm::stdlib::sys 2021-09-30 02:19:58 +09:00