Marc Zyngier 12b2905af1 irqchip/gic-v3-its: Honor hypervisor enforced LPI range ...

A recent extension to the GIC architecture allows a hypervisor to
arbitrarily reduce the number of LPIs available to a guest, no
matter what the GIC says about the valid range of IntIDs.

Let's factor in this information when computing the number of
available LPIs

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

2018-07-16 14:22:19 +01:00

..

arm-gic-common.h

irqchip/gic-v3: Advertise GICv4 support to KVM

2017-08-31 15:31:42 +01:00

arm-gic-v3.h

irqchip/gic-v3-its: Honor hypervisor enforced LPI range

2018-07-16 14:22:19 +01:00

arm-gic-v4.h

irqchip/gic-v4: Add forward definition of struct irq_domain_ops

2017-11-13 16:21:33 +00:00

arm-gic.h

KVM: arm/arm64: vgic: Don't populate multiple LRs with the same vintid

2018-03-14 18:31:04 +00:00

arm-vic.h

…

chained_irq.h

…

ingenic.h

…

irq-bcm2836.h

irqchip: bcm2836: Move SMP startup code to arch/arm (v2)

2017-09-25 11:52:26 -07:00

irq-omap-intc.h

irqchip/irq-omap-intc: Remove omap3_init_irq()

2017-10-16 21:05:14 +02:00

irq-partition-percpu.h

irqchip: Add per-cpu interrupt partitioning library

2016-05-02 13:42:51 +02:00

irq-sa11x0.h

…

mmp.h

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

2017-11-02 11:10:55 +01:00

mxs.h

…

versatile-fpga.h

License cleanup: add SPDX GPL-2.0 license identifier to files with no license

2017-11-02 11:10:55 +01:00

xtensa-mx.h

…

xtensa-pic.h

…