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https://github.com/torvalds/linux
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aca063c902
The original commit8c30b0018f("openrisc: Add jump label support") copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remote icaches need to be invalidated otherwise static key's may remain state after updating. Fix SMP cache syncing by: 1. Properly invalidate remote core icaches on SMP systems by using icache_all_inv. The old code uses kick_all_cpus_sync() which runs a no-op IPI function call on remote CPU's which does execute a lot of code and flushes many cache lines in the process, but does not flush all and it's not correct on OpenRISC. 2. For architectures that do not have WRITETHROUGH caches be sure to flush the dcache after patching. To test this I first reproduced the issue using a custom test module [0]. The test confirmed that some icache lines maintained stale static_key code sequences after calling static_branch_enable(). After this patch there are no longer jump_label coherency issues. [0] https://github.com/stffrdhrn/or1k-utils/tree/master/tests/smp_static_key_test Cc: stable@vger.kernel.org # depends on openrisc: Add icache_all_inv Fixes:8c30b0018f("openrisc: Add jump label support") Signed-off-by: Stafford Horne <shorne@gmail.com>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2020 SiFive
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* Copyright (C) 2025 Chen Miao
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*/
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/uaccess.h>
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#include <asm/insn-def.h>
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#include <asm/cacheflush.h>
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#include <asm/page.h>
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#include <asm/fixmap.h>
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#include <asm/text-patching.h>
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#include <asm/sections.h>
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static DEFINE_RAW_SPINLOCK(patch_lock);
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static __always_inline void *patch_map(void *addr, int fixmap)
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{
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uintptr_t uaddr = (uintptr_t) addr;
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phys_addr_t phys;
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if (core_kernel_text(uaddr)) {
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phys = __pa_symbol(addr);
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} else {
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struct page *page = vmalloc_to_page(addr);
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BUG_ON(!page);
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phys = page_to_phys(page) + offset_in_page(addr);
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}
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return (void *)set_fixmap_offset(fixmap, phys);
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}
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static void patch_unmap(int fixmap)
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{
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clear_fixmap(fixmap);
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}
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static int __patch_insn_write(void *addr, u32 insn)
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{
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void *waddr = addr;
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unsigned long flags = 0;
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int ret;
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raw_spin_lock_irqsave(&patch_lock, flags);
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waddr = patch_map(addr, FIX_TEXT_POKE0);
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ret = copy_to_kernel_nofault(waddr, &insn, OPENRISC_INSN_SIZE);
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if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
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local_dcache_range_flush((unsigned long)waddr,
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(unsigned long)waddr + OPENRISC_INSN_SIZE);
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local_icache_range_inv((unsigned long)waddr,
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(unsigned long)waddr + OPENRISC_INSN_SIZE);
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patch_unmap(FIX_TEXT_POKE0);
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raw_spin_unlock_irqrestore(&patch_lock, flags);
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return ret;
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}
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/*
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* patch_insn_write - Write a single instruction to a specified memory location
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* This API provides a single-instruction patching, primarily used for runtime
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* code modification.
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* By the way, the insn size must be 4 bytes.
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*/
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int patch_insn_write(void *addr, u32 insn)
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{
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u32 *tp = addr;
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int ret;
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if ((uintptr_t) tp & 0x3)
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return -EINVAL;
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ret = __patch_insn_write(tp, insn);
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return ret;
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}
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